diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-18 20:42:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-20 01:27:36 +0000 |
| commit | ce60fb1d6305744ea7655c57b1c1efbf8451a6bc (patch) | |
| tree | 922a3a9de3b57b4cb4acbf80b322c4807457b293 /src/soc/amd/cezanne | |
| parent | 5b94f9a663b08ff73466c0ee97594367729ae919 (diff) | |
soc/amd: factor out non-CAR romstage to common code
Since the romstage code is very similar between all AMD non-CAR SoCs,
factor out a common romstage implementation. All SoCs that select
SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so
this Kconfig option can be used to determine whether to make that call.
In the FSP case, amd_fsp_early_init gets called, while in the case of an
implementation that doesn't rely on an FSP to do the initialization,
cbmem_initialize_empty gets called to set up CBMEM which otherwise would
be done inside the FSP driver code. Since only some SoCs call
fch_disable_legacy_dma_io again in romstage right after
amd_fsp_early_init, introduce the new
SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the
SoCs can specify if this call is needed or not.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 28 |
3 files changed, 1 insertions, 29 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 42a7bf335e..0ef658c10f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -77,6 +77,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_BLOCK_XHCI + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 044d33ead2..dedf98c4bd 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += early_fch.c bootblock-y += espi_util.c romstage-y += fsp_m_params.c -romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c deleted file mode 100644 index 6b84728ad1..0000000000 --- a/src/soc/amd/cezanne/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/fsp.h> -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - amd_fsp_early_init(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} |