diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-05-24 20:25:58 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-06-22 12:30:15 +0000 |
| commit | 27d6299d51744bda549b7764b8fde909ad812e33 (patch) | |
| tree | c30a57ff78e57c9c79a74c4b27cc6e5dfbc94a49 /src/soc/amd/cezanne | |
| parent | 37b161fb96c602765fef9f64415f809830b915a4 (diff) | |
device/resource: Add _kb postfix for resource allocators
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/root_complex.c | 16 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/uart.c | 2 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 1381df3fd6..075f1a1f76 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -118,27 +118,27 @@ static void read_resources(struct device *dev) pci_dev_read_resources for it */ /* 0x0 - 0x9ffff */ - ram_resource(dev, idx++, 0, 0xa0000 / KiB); + ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_resource(dev, idx++, (1 * MiB) / KiB, + ram_resource_kb(dev, idx++, (1 * MiB) / KiB, (early_reserved_dram_start - (1 * MiB)) / KiB); /* DRAM reserved for early coreboot usage */ - reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, + reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB, (early_reserved_dram_end - early_reserved_dram_start) / KiB); /* * top of DRAM consumed early - low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_resource(dev, idx++, early_reserved_dram_end / KiB, + ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); mmconf_resource(dev, idx++); @@ -162,9 +162,9 @@ static void read_resources(struct device *dev) continue; /* Done separately */ if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) - ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) - reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else printk(BIOS_ERR, "failed to set resources for type %d\n", res->type); diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index cf535d7aec..7917ebd195 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -87,7 +87,7 @@ static void uart_enable(struct device *dev) static void uart_read_resources(struct device *dev) { - mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); + mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); } struct device_operations cezanne_uart_mmio_ops = { |