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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-22 23:50:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:16:09 +0000 |
| commit | f09221c033a27d87f39ab074ee53a109a861f096 (patch) | |
| tree | 8169addbced165c5e79147b1a1fa22f7a226e602 /src/soc/amd/cezanne | |
| parent | 57419de1879ca5d40669fb2690428bc0e0addb31 (diff) | |
soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRS
This option will make the ramstage MTRR core set the additional bits in
the fixed MTRRs that need to be set on AMD CPUs to enable caching.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94bca61acfc6e38a6d808eb5020537b4e8596178
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 15a40377cd..08d8397bf6 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -29,6 +29,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select UDK_2017_BINDING + select X86_AMD_FIXED_MTRRS config CHIPSET_DEVICETREE string |