diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-05 15:53:04 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-07 18:08:07 +0000 |
| commit | b9e8044b28155747024bc5d74d9ea55ed94a60e3 (patch) | |
| tree | a06a523d9e17226aec7fb1db859be781d0944f96 /src/soc/amd/cezanne | |
| parent | 899be1b3529b391c430504589649f0ec9452a1d9 (diff) | |
soc/amd/cezanne/romstage: Store early dram region
Needed so we can reserve the memory.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index c7e7e5cba4..773c6a97d5 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <amdblocks/memmap.h> #include <arch/cpu.h> #include <console/console.h> #include <console/uart.h> @@ -33,5 +34,7 @@ asmlinkage void car_stage_entry(void) fsp_memory_init(acpi_is_wakeup_s3()); + memmap_stash_early_dram_usage(); + run_ramstage(); } |