diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 01:16:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:15:59 +0000 |
| commit | 57419de1879ca5d40669fb2690428bc0e0addb31 (patch) | |
| tree | 343796e13d08b9a622e83fcd98942a2152970381 /src/soc/amd/cezanne | |
| parent | 8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (diff) | |
soc/amd/cezanne: add basic romstage
This currently only initializes the console, calls into the FSP driver
that then calls into FSP-M and then jumps to ramstage after the FSP-M
returns. Right now, this mainly unblocks the FSP-M development.
Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 52ff0f8e41..509addfa52 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> +#include <console/console.h> #include <fsp/api.h> +#include <program_loading.h> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { @@ -9,4 +11,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) asmlinkage void car_stage_entry(void) { + post_code(0x40); + console_init(); + + post_code(0x41); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fsp_memory_init(false); /* no S3 resume yet */ + + run_ramstage(); } |