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authorFelix Held <felix-coreboot@felixheld.de>2023-07-18 23:33:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-07-25 13:34:23 +0000
commitd6656bed832b5cf42e86bac286c3cfa5ba30f16d (patch)
treea619200d903168e8e3e2a18a7432aec0894c6a02 /src/soc/amd/cezanne
parentb8b0c66cffe1edaf2ddff66c17943d0f5d774330 (diff)
soc/amd/*/root_complex: don't report root complex IOAPIC resource twice
Since the per PCI root IOAPIC is now reported as domain MMIO resource and the IVRS code now again probes for the IOAPIC resource on the domain device, the IOAPIC resource doesn't need to be reported as resource of the northbridge PCI device any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/root_complex.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 0ddce95a8a..cea3b20dd5 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -143,9 +143,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
- /* GNB IOAPIC resource */
- mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
-
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);