diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-12-06 10:53:54 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 17:52:03 +0000 |
| commit | c7ab9f410cfea6bd6260ecb8ac336f87f4cf3736 (patch) | |
| tree | 2615eda091f426dac7470e02b39ed8b05372870b /src/soc/amd/cezanne | |
| parent | 9a185e5bfe1a26551f59c5b63c6f3625b184900f (diff) | |
soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states#
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit.
This change makes sure we clear the PM/GPE blocks are cleared before
enabling the SCI_EN bit.
BUG=b:172021431
TEST=Boot guybrush and morphius to OS and verify suspend resume still
works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/smihandler.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 7653836151..2549ef8e2e 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -23,6 +23,7 @@ static void fch_apmc_smi_handler(void) switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: |