diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-10-29 13:31:54 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-04 01:00:27 +0000 |
| commit | bcb610a5595f7ff99129dfbaff9c6b4e1b5c3584 (patch) | |
| tree | fd9197d90effa73f4b95bfb45804179db8034981 /src/soc/amd/cezanne | |
| parent | b6877e401a8686ac6dfcebb1184ebdfabad6f3e6 (diff) | |
soc/amd: Specify memory types supported by each chip
This change disables support for memory types not used by each of the
chips. This will in turn remove the files for those memory types from
the platform builds.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 11f80766e8..1630df2e72 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -28,6 +28,9 @@ config SOC_SPECIFIC_OPTIONS select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select NO_DDR5 + select NO_DDR3 + select NO_DDR2 select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING @@ -76,6 +79,8 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING + select USE_DDR4 + select USE_LPDDR4 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |