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authorMartin Roth <gaumless@gmail.com>2023-08-18 16:28:29 -0600
committerMartin L Roth <gaumless@gmail.com>2023-08-26 21:39:22 +0000
commit8fc68816a96c6fdfc7a35ec1c68b681b03decc06 (patch)
tree4316aa27580c58bafde7d17b5f2e60756ec2d37a /src/soc/amd/cezanne
parent7687e7767f2d2321b57fa8eab68b7e954e57ad42 (diff)
soc/amd: Move psp_transfer.h out of each SOC into common
The psp_transfer.h file was the same under all SoCs, and is really tied to the file common/vboot/transfer.c, not the SOC. This patch makes an include directory under vboot to put the header into and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes the header file available to all platforms, so that new chips that don't use the psp_verstage don't have to make a psp_transfer.h file just to satisfy the compiler. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/include/soc/psp_transfer.h62
-rw-r--r--src/soc/amd/cezanne/smihandler.c2
2 files changed, 1 insertions, 63 deletions
diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h
deleted file mode 100644
index f81785ec11..0000000000
--- a/src/soc/amd/cezanne/include/soc/psp_transfer.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_CEZANNE_PSP_TRANSFER_H
-#define AMD_CEZANNE_PSP_TRANSFER_H
-
-# if (CONFIG_CMOS_RECOVERY_BYTE != 0)
-# define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE
-# elif CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)
-# error "Must set CONFIG_CMOS_RECOVERY_BYTE"
-# endif
-
-#define CMOS_RECOVERY_MAGIC_VAL 0x96
-
-#define TRANSFER_INFO_SIZE 64
-#define TIMESTAMP_BUFFER_SIZE 0x200
-
-#define TRANSFER_MAGIC_VAL 0x50544953
-
-/* Bit definitions for the psp_info field in the PSP transfer_info_struct */
-#define PSP_INFO_PRODUCTION_MODE 0x00000001UL
-#define PSP_INFO_PRODUCTION_SILICON 0x00000002UL
-#define PSP_INFO_VALID 0x80000000UL
-
-/* Area for things that would cause errors in a linker script */
-#if !defined(__ASSEMBLER__)
-#include <stdint.h>
-
-struct transfer_info_struct {
- uint32_t magic_val; /* Identifier */
- uint32_t struct_bytes; /* Size of this structure */
- uint32_t buffer_size; /* Size of the transfer buffer area */
-
- /* Offsets from start of transfer buffer */
- uint32_t workbuf_offset;
- uint32_t console_offset;
- uint32_t timestamp_offset;
- uint32_t fmap_offset;
-
- uint32_t unused1[5];
-
- /* Fields reserved for the PSP */
- uint64_t timestamp; /* Offset 0x30 */
- uint32_t psp_unused; /* Offset 0x38 */
- uint32_t psp_info; /* Offset 0x3C */
-};
-
-_Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE,
- "TRANSFER_INFO_SIZE is incorrect");
-
-/* Make sure the PSP transferred information over to x86 side. */
-int transfer_buffer_valid(const struct transfer_info_struct *ptr);
-/* Verify vboot work buffer is valid in transfer buffer */
-void verify_psp_transfer_buf(void);
-/* Display the transfer block's PSP_info data */
-void show_psp_transfer_info(void);
-/* Replays the pre-x86 cbmem console into the x86 cbmem console */
-void replay_transfer_buffer_cbmemc(void);
-/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */
-void boot_with_psp_timestamp(uint64_t base_timestamp);
-
-#endif
-#endif /* AMD_CEZANNE_PSP_TRANSFER_H */
diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
index 61f5099362..2c5489f03b 100644
--- a/src/soc/amd/cezanne/smihandler.c
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -13,7 +13,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <elog.h>
-#include <soc/psp_transfer.h>
+#include <psp_verstage/psp_transfer.h>
#include <soc/smi.h>
#include <soc/smu.h>
#include <soc/southbridge.h>