diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-12 09:21:51 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-07-14 17:54:36 +0000 |
| commit | 73e0f18b35f154dc54994474448df283f51d659d (patch) | |
| tree | c1cf56b1e1097ac969176186bc8703f9c9ba01cc /src/soc/amd/cezanne | |
| parent | 2c7080692a281d64a99aeb8db7b65b33b83c3f90 (diff) | |
soc/amd/cezanne: Move APOB update into ramstage
There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b64fb4bbe5..9e863c3966 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <amdblocks/acpimmio.h> -#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -25,7 +24,6 @@ asmlinkage void car_stage_entry(void) fill_chipset_state(); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_apob_cache(); /* Fixup settings FSP-M should not be changing */ fch_disable_legacy_dma_io(); |