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authorFelix Held <felix-coreboot@felixheld.de>2023-09-20 18:51:27 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-09-21 18:26:12 +0000
commit63e77b025251afba6202056f688854be38b6e28d (patch)
tree8e14ce4c925f4ae77ff895f907437555d540c5fa /src/soc/amd/cezanne
parent05a3c1de3816c9aecfb34e1273547d27a712c5e2 (diff)
soc/amd/*/cpu: factor out common noncar mp_init_cpus
Since all non-CAR AMD SoCs have the same mp_init_cpus implementation, factor it out and move it to a common location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/cpu.c24
1 files changed, 0 insertions, 24 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index c1cf663336..2c3100fc81 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,39 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
-#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <soc/cpu.h>
-#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
-/* MP and SMM loading initialization */
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
- extern const struct mp_ops amd_mp_ops_with_smm;
- if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POSTCODE_HW_INIT_FAILURE,
- "mp_init_with_smm failed. Halting.\n");
-
- /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
- mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
- FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
-
- /* SMMINFO only needs to be set up when booting from S5 */
- if (!acpi_is_wakeup_s3())
- apm_control(APM_CNT_SMMINFO);
-}
-
static void zen_2_3_init(struct device *dev)
{
check_mca();