soc/amd/*/i2c: factor out common I2C pad configuration

The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO  for future improvements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

4 files changed, 5 insertions, 44 deletions

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 620c650ba1..f0b7c272d4 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -50,6 +50,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index d007a84c98..1e59153ef5 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -4,6 +4,7 @@
 #define CEZANNE_CHIP_H
 
 #include <amdblocks/chip.h>
+#include <amdblocks/i2c.h>
 #include <gpio.h>
 #include <soc/i2c.h>
 #include <soc/southbridge.h>
@@ -15,7 +16,7 @@ struct soc_amd_cezanne_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
-	u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT];
+	struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
 
 	/* Enable S0iX support */
 	bool s0ix_enable;
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c
index 1fcab6a0db..bf47b81462 100644
--- a/src/soc/amd/cezanne/i2c.c
+++ b/src/soc/amd/cezanne/i2c.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <amdblocks/acpimmio.h>
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
@@ -36,24 +35,11 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	const struct soc_amd_cezanne_config *config = config_of_soc();
-	uint32_t pad_ctrl;
 
-	if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
+	if (bus >= ARRAY_SIZE(config->i2c_pad))
 		return;
 
-	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
-	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
-	pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus];
-
-	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
-	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
-		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
-	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+	fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 9c68d38352..4e44b89fe4 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -112,33 +112,6 @@
 #define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
 #define   BP_X48M0_S0I3_DIS		BIT(4)
 #define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
-#define MISC_I2C0_PAD_CTRL		0xd8
-#define MISC_I2C1_PAD_CTRL		0xdc
-#define MISC_I2C2_PAD_CTRL		0xe0
-#define MISC_I2C3_PAD_CTRL		0xe4
-#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
-#define     I2C_PAD_CTRL_RX_SHIFT	4
-#define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
-#define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
-#define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
-#define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define   I2C_PAD_CTRL_FALLSLEW_EN	BIT(9)
-#define   I2C_PAD_CTRL_SPIKE_RC_EN	BIT(10)
-#define   I2C_PAD_CTRL_SPIKE_RC_SEL	BIT(11) /* 0 = 50ns, 1 = 20ns */
-#define   I2C_PAD_CTRL_CAP_DOWN		BIT(12)
-#define   I2C_PAD_CTRL_CAP_UP		BIT(13)
-#define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
-#define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
-#define   I2C_PAD_CTRL_SPARE0		BIT(17)
-#define   I2C_PAD_CTRL_SPARE1		BIT(18)
 
 void fch_pre_init(void);
 void fch_early_init(void);