src/soc/amd/cezanne: enable clock gating

Enabling clock gating for CGPLL to lower power consumption in S3
and S0i3 states. See also: Cezanne PPR chapter 7, rev 3.03.

BUG=b:185273565
TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating
enabled and suspend_stress_test works.

Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

2 files changed, 34 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index ac79cc9e11..dd19c310bc 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -169,6 +169,28 @@ static void gpp_clk_setup(void)
 	misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
 }
 
+static void cgpll_clock_gate_init(void)
+{
+	uint32_t t;
+
+	t = misc_read32(MISC_CLKGATEDCNTL);
+	t |= ALINKCLK_GATEOFFEN;
+	t |= BLINKCLK_GATEOFFEN;
+	t |= XTAL_PAD_S3_TURNOFF_EN;
+	t |= XTAL_PAD_S5_TURNOFF_EN;
+	misc_write32(MISC_CLKGATEDCNTL, t);
+
+	t = misc_read32(MISC_CGPLL_CONFIGURATION0);
+	t |= USB_PHY_CMCLK_S3_DIS;
+	t |= USB_PHY_CMCLK_S0I3_DIS;
+	t |= USB_PHY_CMCLK_S5_DIS;
+	misc_write32(MISC_CGPLL_CONFIGURATION0, t);
+
+	t = pm_read32(PM_ISACONTROL);
+	t |= ABCLKGATEEN;
+	pm_write32(PM_ISACONTROL, t);
+}
+
 void fch_init(void *chip_info)
 {
 	fch_init_resets();
@@ -181,6 +203,7 @@ void fch_init(void *chip_info)
 
 	gpp_clk_setup();
 	fch_clk_output_48Mhz();
+	cgpll_clock_gate_init();
 }
 
 void fch_final(void *chip_info)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 88137075c7..addb850621 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -6,6 +6,8 @@
 #include <soc/iomap.h>
 
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PM_ISACONTROL			0x04
+#define   ABCLKGATEEN			BIT(16)
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define PWR_RESET_CFG			0x10
@@ -82,6 +84,15 @@
 #define   GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
 #define   GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
 
+#define MISC_CLKGATEDCNTL		0x2c
+#define   ALINKCLK_GATEOFFEN		BIT(16)
+#define   BLINKCLK_GATEOFFEN		BIT(17)
+#define   XTAL_PAD_S3_TURNOFF_EN	BIT(20)
+#define   XTAL_PAD_S5_TURNOFF_EN	BIT(21)
+#define MISC_CGPLL_CONFIGURATION0	0x30
+#define   USB_PHY_CMCLK_S3_DIS		BIT(8)
+#define   USB_PHY_CMCLK_S0I3_DIS	BIT(9)
+#define   USB_PHY_CMCLK_S5_DIS		BIT(10)
 #define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
 #define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
 #define MISC_I2C0_PAD_CTRL		0xd8