diff options
| author | Kangheui Won <khwon@chromium.org> | 2022-01-25 17:56:43 +1100 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-01 22:31:56 +0000 |
| commit | 506ca3ef4e78d3b32cddfe81eeaa10af86fd57b6 (patch) | |
| tree | 7b71c44aee5c8dcbc2cdf85a3cba363db4367c46 /src/soc/amd/cezanne | |
| parent | 894f6f8229a7bb479c523ce4bcbf927f2d1f1d5b (diff) | |
psp_verstage: add new svc for cezanne
Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index e04c702518..78f71260a4 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -133,3 +133,10 @@ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); return retval; } + +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); + return retval; +} |