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authorFelix Held <felix-coreboot@felixheld.de>2023-02-06 21:13:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-02-08 15:52:56 +0000
commit3ecf377e305e1a026ddfa66adf800a28993f4075 (patch)
treeb9b54f2a6b1ca3227766bd21573925b3aaf95a79 /src/soc/amd/cezanne
parent8f705b9fad1f59ea370bf55c8b3b901dd89357ed (diff)
soc/amd: use CPUID_FROM_FMS macro instead of magic numbers
Port over the remaining AMD SoCs to use CPUID_FROM_FMS. The Glinda CPUID still needs to be updated to the actual CPUID, but for now just change it to use CPUID_FROM_FMS. TEST=Resulting image of timeless build for Gardenia (Stoneyridge), Majolica (Cezanne), Chausie (Mendocino), Mayan (Phoenix) and Birman (Glinda) don't change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia508f857d06f3c15e3ac9f813302471348ce3d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72862 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/include/soc/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h
index 926fd05de7..0239e19fe9 100644
--- a/src/soc/amd/cezanne/include/soc/cpu.h
+++ b/src/soc/amd/cezanne/include/soc/cpu.h
@@ -3,7 +3,7 @@
#ifndef AMD_CEZANNE_CPU_H
#define AMD_CEZANNE_CPU_H
-#define CEZANNE_A0_CPUID 0x00a50f00
+#define CEZANNE_A0_CPUID CPUID_FROM_FMS(0x19, 0x50, 0)
#define CEZANNE_VBIOS_VID_DID 0x10021638
#define BARCELO_VBIOS_VID_DID 0x100215e7