diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-08 17:21:04 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 18:42:59 +0000 |
| commit | 4be064a1d8b3693954c637e578cf3d6aec625105 (patch) | |
| tree | 08d07975e6a0a0c7aaf2d771232f2ed9970e41d0 /src/soc/amd/cezanne | |
| parent | 34cf0732209e7b9fefc115536719473155e430ea (diff) | |
soc/amd/cezanne: add common SMBus code to build
Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.
Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 9 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 8 |
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index fe248c6097..be45de4145 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,11 +13,13 @@ config SOC_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H config EARLY_RESERVED_DRAM_BASE diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h new file mode 100644 index 0000000000..96313eaf3c --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_IOMAP_H +#define AMD_CEZANNE_IOMAP_H + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 + +#endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h new file mode 100644 index 0000000000..0f26ff0807 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_SOUTHBRIDGE_H +#define AMD_CEZANNE_SOUTHBRIDGE_H + +#include <soc/iomap.h> + +#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ |