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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-22 13:35:35 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 15:33:00 +0000 |
| commit | 0589e3ce7f5ba7c7b756fe748c1d7950e495dd84 (patch) | |
| tree | df5900f8ae5dc1f0c1a0a5c4b9a90951573eb466 /src/soc/amd/cezanne/romstage.c | |
| parent | ff730feaccd625045e2bf3e1622898ac850d7a18 (diff) | |
soc/amd/common: Refactor single GPIO programming
Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.
Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/romstage.c')
0 files changed, 0 insertions, 0 deletions