diff options
| author | Martin Roth <gaumless@gmail.com> | 2023-02-01 14:27:18 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-04 03:23:04 +0000 |
| commit | 440c8236757de32c6cfd41ef67696f9f09992986 (patch) | |
| tree | c084c1d1725221cde44ef2c03ddd5b1d74de066a /src/soc/amd/cezanne/reset.c | |
| parent | c46c15b5920bf8378c333f862a8f5766cf104c85 (diff) | |
soc/amd: Use common reset code for CZN & MDN SoCs
This switches the Cezanne & Mendocino SoCs to use the common reset code.
This patch does not change any behavior on those chips.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/reset.c')
| -rw-r--r-- | src/soc/amd/cezanne/reset.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c deleted file mode 100644 index 1360bd53b1..0000000000 --- a/src/soc/amd/cezanne/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} |