diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-02-04 16:39:11 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-02-08 05:38:27 +0000 |
| commit | 168798a53e43349f07597210ddcdcfd85d8ea9cf (patch) | |
| tree | 8ac8a4573a7e1bca8ace9905c8bf2fc6f6e0f1f9 /src/soc/amd/cezanne/mca.c | |
| parent | 2904aeabad4db6797130b60f386d1feb6dfa1949 (diff) | |
mb/intel/mtlrvp: Add ACPI configuration for USB2/3 ports
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per
schematics. This helps in generating corresponding ACPI code at runtime
that includes port information.
BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP. Connect USB device and check if
corresponding enumeration of USB device (14.0) is observed on executing
lspci.
00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01)
00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie150247661322e3944be15dc70f66033266d8aac
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/mca.c')
0 files changed, 0 insertions, 0 deletions