diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 20:52:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 23:44:24 +0000 |
| commit | bb42f67240c7d69a8784a03565da1239908fe402 (patch) | |
| tree | 0c3faf0ff3e61859228e7e826831a2009e64a986 /src/soc/amd/cezanne/include | |
| parent | 42d8cbf4d28fb13169a413c16507495f18fb9bab (diff) | |
soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 113395e954..9c68d38352 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -116,6 +116,7 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) #define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc #define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) |