diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 16:30:55 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:15:10 +0000 |
| commit | a63f859553a29842fd8d65ae8a6523cd429a5f85 (patch) | |
| tree | ccf769584dc8e02611be5123f2721f41a21023f3 /src/soc/amd/cezanne/include | |
| parent | c08d804f01d88ac028c7271f0efed07373c3bc97 (diff) | |
soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freq
Factor out the get_pstate_core_freq function from the SoC's acpi.c files
to both avoid duplication and to also be able to use the same function
in the TSC frequency calculation in a follow-up patch. The family 17h
and 19h SoCs use the same frequency encoding in the P state MSRs while
the family 1Ah SoCs use a different encoding. The family 15h and 16h
SoCs use another encoding, but since this isn't implemented in
Stoneyridge's acpi.c, this will be added in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 79ebc7eee5..0fba3e6d83 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -17,11 +17,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_FREQ_DIV_MIN 0x8 -#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A -#define PSTATE_DEF_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_CORE_FREQ_BASE 25 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 |