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authorRaul E Rangel <rrangel@chromium.org>2021-02-11 16:43:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-02-22 07:29:01 +0000
commit980721b3ed253e699c4a208040c76045abb3d964 (patch)
tree2185636444cde4845c453337b8cb8565ec71f214 /src/soc/amd/cezanne/include
parent1156acbb7eaae3f23e67e05512068e183eea6375 (diff)
soc/amd/cezanne/acpi: Add MMIO devices
The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
-rw-r--r--src/soc/amd/cezanne/include/soc/iomap.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 0d59c2c47c..3a84fae4c7 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -3,6 +3,8 @@
#ifndef AMD_CEZANNE_IOMAP_H
#define AMD_CEZANNE_IOMAP_H
+#if ENV_X86
+
/* MMIO Ranges */
#define SPI_BASE_ADDRESS 0xfec10000
@@ -14,6 +16,11 @@
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
+#define APU_I2C0_BASE 0xfedc2000
+#define APU_I2C1_BASE 0xfedc3000
+#define APU_I2C2_BASE 0xfedc4000
+#define APU_I2C3_BASE 0xfedc5000
+
#define APU_DMAC0_BASE 0xfedc7000
#define APU_DMAC1_BASE 0xfedc8000
#define APU_UART0_BASE 0xfedc9000
@@ -21,6 +28,8 @@
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
+#endif /* ENV_X86 */
+
/* I/O Ranges */
#define NCP_ERR 0x00f0
#define ACPI_IO_BASE 0x0400