diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-13 03:06:21 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 15:41:42 +0000 |
| commit | 8a3d4d5ec6260a2db9cfda954860ed525bb67134 (patch) | |
| tree | b9d7574fbdd5d057547e4689017dd922701d70d2 /src/soc/amd/cezanne/include | |
| parent | 91ef92525d8a9a0e83be8d91eb5e83b1cab58008 (diff) | |
soc/amd/cezanne: add console UART support
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/uart.h | 11 |
3 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index b377ee31fb..20f70371f0 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,14 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* FCH AL2AHB Registers */ +#define ALINK_AHB_ADDRESS 0xfedc0000 + +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 + /* MMIO Ranges */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index ec4f3a78e5..7fb61b67e2 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -10,6 +10,8 @@ #define TOGGLE_ALL_PWR_GOOD (1 << 1) #define PM_ACPI_SMI_CMD 0x6a +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ + /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT (1 << 7) /* Write-once */ diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h new file mode 100644 index 0000000000..9b99cd4b24 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H + +#include <types.h> + +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ +void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ + +#endif /* AMD_PICASSO_UART_H */ |