diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-10 00:00:47 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-20 19:52:27 +0000 |
| commit | da02a82f221897e75fe046f9a48eb45ba5409d05 (patch) | |
| tree | 07a727bcc2c539c87ad0c953835f9005ae77dd91 /src/soc/amd/cezanne/include | |
| parent | 659e154d68a5dd706e1d99513a9a7947ab3b87fc (diff) | |
soc/amd/cezanne: introduce and use pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If92a4773c669ac2df45396eee52f6de780adbdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 5a0bac1231..8163cf8000 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -4,19 +4,22 @@ #define AMD_CEZANNE_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 -#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) -#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 -#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT) -#define PSTATE_DEF_LO_CORE_VID_SHIFT 14 -#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT) -#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8 -#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT) +union pstate_msr { + struct { + uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */ + uint64_t cpu_dfs_id : 6; /* [ 8..13] */ + uint64_t cpu_vid_0_7 : 8; /* [14..21] */ + uint64_t idd_value : 8; /* [22..29] */ + uint64_t idd_div : 2; /* [30..31] */ + uint64_t : 31; /* [32..62] */ + uint64_t pstate_en : 1; /* [63..63] */ + }; + uint64_t raw; +}; + #define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8 #define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A #define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0 -#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ |