diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 02:01:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 17:44:42 +0000 |
| commit | 44f41537af4022ce8d8c4fadb6b690b3ec6f8c61 (patch) | |
| tree | d28b4299b86f996f768f723c2a844a0146c3c606 /src/soc/amd/cezanne/include | |
| parent | e04a18fc25cfb28690cd7dbd3302a63436b1ccd2 (diff) | |
soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/reset.h | 9 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 7 |
3 files changed, 18 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 96313eaf3c..4d47f7ed57 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_IOMAP_H /* I/O Ranges */ -#define SMB_BASE_ADDR 0xb00 +#define NCP_ERR 0x00f0 +#define SMB_BASE_ADDR 0x0b00 #endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h new file mode 100644 index 0000000000..4cb94ced02 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/reset.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_RESET_H +#define AMD_CEZANNE_RESET_H + +void set_warm_reset_flag(void); +int is_warm_reset(void); + +#endif /* AMD_CEZANNE_RESET_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2456ebc6f9..03ee2bb2d1 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -5,6 +5,13 @@ #include <soc/iomap.h> +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) + +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT (1 << 7) /* Write-once */ + void fch_pre_init(void); void fch_early_init(void); |