diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-03 21:38:14 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 22:05:59 +0000 |
| commit | 7e703d77b2cb2189863d2a2e87f7de2913e20307 (patch) | |
| tree | 2667898e7a0ab41ad613bf26129e03b071513592 /src/soc/amd/cezanne/fch.c | |
| parent | 757d645cb069f1759303467efb9753fcdd847da4 (diff) | |
soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/fch.c')
| -rw-r--r-- | src/soc/amd/cezanne/fch.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index f853ecee93..5fb4f0ab98 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -1,9 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> +#include <assert.h> +#include <soc/iomap.h> #include <soc/southbridge.h> +static void fch_init_acpi_ports(void) +{ + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* TODO: add code for SMI handler case */ + dead_code(); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + void fch_init(void *chip_info) { + fch_init_acpi_ports(); } void fch_final(void *chip_info) |