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| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2021-12-07 19:26:47 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-08 16:05:55 +0000 |
| commit | 9a185e5bfe1a26551f59c5b63c6f3625b184900f (patch) | |
| tree | 0980032f273f7eba7bceb703831ab1b4aeb0df6a /src/soc/amd/cezanne/chipset.cb | |
| parent | 289e2f6a64c5cce10edd84f391025d4083ee651f (diff) | |
mb/google/brya/var/primus: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue.
BUG=b:209568644
BRANCH=none
TEST=build coreboot and system boot into OS.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/chipset.cb')
0 files changed, 0 insertions, 0 deletions