diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-10-05 22:12:02 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-13 19:43:10 +0000 |
| commit | b171f768127d9bbc377ba97fd097ba0dcd4e148d (patch) | |
| tree | e7e93b0bd3984f392b4e003dcd401a8a513f78a8 /src/soc/amd/cezanne/chipset.cb | |
| parent | 987ec8837ac8c5288a92af52c9bdd51f9019db3c (diff) | |
soc/amd/*: Hook up GPP bridges ops to devicetree
This removes the need for a PCI driver.
Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/chipset.cb')
| -rw-r--r-- | src/soc/amd/cezanne/chipset.cb | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index b0ebde59d9..7fd207d4a7 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -13,16 +13,17 @@ chip soc/amd/cezanne device pci 01.3 alias gpp_gfx_bridge_2 off end device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end - device pci 02.7 alias gpp_bridge_6 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -81,12 +82,14 @@ chip soc/amd/cezanne device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio end |