diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 22:11:52 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 23:46:00 +0000 |
| commit | 556d1cc17f34615e3a08ccc9a48820a304a789a8 (patch) | |
| tree | 832a9c4ea64316f665dc3966a478dc44c4838e67 /src/soc/amd/cezanne/chip.h | |
| parent | bb42f67240c7d69a8784a03565da1239908fe402 (diff) | |
soc/amd/*/i2c: factor out common I2C pad configuration
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index d007a84c98..1e59153ef5 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -4,6 +4,7 @@ #define CEZANNE_CHIP_H #include <amdblocks/chip.h> +#include <amdblocks/i2c.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -15,7 +16,7 @@ struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; |