diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-08 23:18:19 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 15:42:34 +0000 |
commit | 62ef88f3e902c92ca9e0c20bd6abf094468eafed (patch) | |
tree | 98c8fa22e9094396724f16fe92dfc2589180a848 /src/soc/amd/cezanne/aoac.c | |
parent | 35e1298cb51ec91116d2d49f1a905b2ddb7b72cc (diff) |
soc/amd/cezanne: add AOAC support
Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/aoac.c')
-rw-r--r-- | src/soc/amd/cezanne/aoac.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/aoac.c b/src/soc/amd/cezanne/aoac.c new file mode 100644 index 0000000000..9c58bb5442 --- /dev/null +++ b/src/soc/amd/cezanne/aoac.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> +#include <soc/southbridge.h> +#include <delay.h> + +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : -1) +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. The console UART is handled separately from this table. + * + * TODO: Find out which I2C controllers we really need to enable here. + */ +const static unsigned int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_ESPI, +}; + +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + +void enable_aoac_devices(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); + + /* Wait for AOAC devices to indicate power and clock OK */ + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + wait_for_aoac_enabled(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} |