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authorFelix Held <felix-coreboot@felixheld.de>2023-05-04 23:17:44 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-05-08 13:03:14 +0000
commitdbfb6b92654f1fbc8799c46f142e31deea73fd9d (patch)
tree3ed770cece6e52b04108ed33e7d9a67f6db9c7d4 /src/soc/amd/cezanne/acpi
parentdeebd9466f3fab66fe6e5f4ebbbc254c7d1cea0b (diff)
soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OS
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates that the device should be shown in the user interface. This ports commit c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS") forward from Stoneyridge to the newer AMD SoCs. TEST=On Mandolin the PCI Express Root Complex now shows up in the device manager on Windows 10 and when switching the view to 'devices by connection', all PCI(e) devices are shown below it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/acpi')
-rw-r--r--src/soc/amd/cezanne/acpi/pci0.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index 93bfb1fccd..fb02a02c3b 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -10,7 +10,7 @@ Device(PCI0) {
}
Method(_STA, 0, NotSerialized) {
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* Operating System Capabilities Method */