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authorRaul E Rangel <rrangel@chromium.org>2021-02-19 10:11:39 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-02-25 23:41:53 +0000
commit8e425b02451c59707b1159d9c72f53f4e5410849 (patch)
tree855ada199781175ed51ffb1ce2d38538a356a014 /src/soc/amd/cezanne/acpi
parent87a1bd696d47f80101e46132efae8cad8cfe5c7e (diff)
soc/amd/cezanne/acpi: Add globalnvs.asl
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/acpi')
-rw-r--r--src/soc/amd/cezanne/acpi/globalnvs.asl20
-rw-r--r--src/soc/amd/cezanne/acpi/soc.asl2
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl
new file mode 100644
index 0000000000..6dd1e6bd2a
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/globalnvs.asl
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/amd/cezanne/include/soc/nvs.h !!!
+ */
+
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ , 8, // 0x00 - Processor Count
+ LIDS, 8, // 0x01 - LID State
+ , 8, // 0x02 - AC Power State
+ CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
+ PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
+ GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
+ TMPS, 8, // 0x17 - Temperature Sensor ID
+ TCRT, 8, // 0x18 - Critical Threshold
+ TPSV, 8, // 0x19 - Passive Threshold
+}
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index c935dc3eea..ecfdef8a24 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -6,6 +6,8 @@ Scope(\_SB) {
#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+ #include "globalnvs.asl"
+
#include "pci_int_defs.asl"
#include "mmio.asl"