soc/amd/cezanne: add skeleton for new SoC

This is based on the minimal example code in soc/example/min86 and was
adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF
support.

In its current state this won't even reach the boot block, but will pass
the build bot. The missing parts for that will be added in future
patches. This is an attempt to not go the usual route to create a copy
of a previous SoC generation and the make changes to the code to work
for the new SoC, but to start from a nearly empty directory and then add
the actual code stage by stage and component by component.

Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
new file mode 100644
index 0000000000..d1d8e97099
--- /dev/null
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
+
+bootblock-y	+= bootblock.c
+
+romstage-y	+= romstage.c
+
+ramstage-y	+= chip.c
+ramstage-y	+= timer.c
+
+CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+
+endif