soc/amd: Use common reset code for CZN & MDN SoCs

This switches the Cezanne & Mendocino SoCs to use the common reset code.
This patch does not change any behavior on those chips.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 5313e0d302..a8474e2364 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -12,18 +12,15 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
-bootblock-y	+= reset.c
 bootblock-y	+= uart.c
 
 verstage-y	+= i2c.c
 verstage_x86-y	+= gpio.c
-verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
 romstage-y	+= gpio.c
 romstage-y	+= i2c.c
-romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
@@ -37,7 +34,6 @@ ramstage-y	+= gpio.c
 ramstage-y	+= graphics.c
 ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
-ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
 ramstage-y	+= xhci.c