soc/amd/cezanne: add GPIO support

This still uses the common GPIO code that supports setting up SMI/SCI
support for the GPIOs in all stages, which will get removed in future
patches, so for now the SoC's gpio.c needs to be included in all stages.

Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 2852b6a652..5ffe06fa05 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -9,14 +9,18 @@ all-y += config.c
 
 bootblock-y	+= bootblock.c
 bootblock-y	+= early_fch.c
+bootblock-y	+= gpio.c
 bootblock-y     += reset.c
 
+verstage_x86-y	+= gpio.c
 verstage_x86-y  += reset.c
 
+romstage-y	+= gpio.c
 romstage-y      += reset.c
 romstage-y	+= romstage.c
 
 ramstage-y	+= chip.c
+ramstage-y	+= gpio.c
 ramstage-y      += reset.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include