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authorFelix Held <felix-coreboot@felixheld.de>2021-01-13 03:06:21 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-14 15:41:42 +0000
commit8a3d4d5ec6260a2db9cfda954860ed525bb67134 (patch)
treeb9d7574fbdd5d057547e4689017dd922701d70d2 /src/soc/amd/cezanne/Makefile.inc
parent91ef92525d8a9a0e83be8d91eb5e83b1cab58008 (diff)
soc/amd/cezanne: add console UART support
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
-rw-r--r--src/soc/amd/cezanne/Makefile.inc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 5ffe06fa05..6a0229cdbc 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -11,17 +11,21 @@ bootblock-y += bootblock.c
bootblock-y += early_fch.c
bootblock-y += gpio.c
bootblock-y += reset.c
+bootblock-y += uart.c
verstage_x86-y += gpio.c
verstage_x86-y += reset.c
+verstage_x86-y += uart.c
romstage-y += gpio.c
romstage-y += reset.c
romstage-y += romstage.c
+romstage-y += uart.c
ramstage-y += chip.c
ramstage-y += gpio.c
ramstage-y += reset.c
+ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include