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authorFelix Held <felix-coreboot@felixheld.de>2021-02-10 16:53:53 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-11 16:18:01 +0000
commitbb4bee8572b6036540e748718851945aa9d36d85 (patch)
tree93756f483b55d17ac386bdbab6964b7ddfdfcfeb /src/soc/amd/cezanne/Kconfig
parent2e97897ea39090493e97c576717b83b6cd41b41c (diff)
soc/amd/cezanne: select soc-specific ACPI functionality
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. The added nvs.h has some currently unused fields, but still having them in the struct aligns it with Picasso and also might reduce the noise in future ACPI patches a bit. When most of the ACPI code for Cezanne has landed, we need to do a cleanup though. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2de60d7cd0..cfdf6ff354 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,6 +13,7 @@ config SOC_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select ACPI_AMD_HARDWARE_SLEEP_VALUES
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
@@ -23,6 +24,7 @@ config SOC_SPECIFIC_OPTIONS
select PLATFORM_USES_FSP2_0
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
+ select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS