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authorRaul E Rangel <rrangel@chromium.org>2021-02-09 14:38:36 -0700
committerMartin Roth <martinroth@google.com>2021-02-12 20:42:35 +0000
commita6529e789f5c460c1b378b3194e795ceb32a5171 (patch)
tree1504d7b36a6ef752b0df8d8ac741c25171e8a266 /src/soc/amd/cezanne/Kconfig
parent77ef99be22e69982a88bd77cafdb1a737fc2f185 (diff)
soc/amd/cezanne: Add PCI IRQ Router definitions
These definitions were identical to picasso. The only thing I changed was that I renamed Misc1 and Misc2 to HPET_L and HPET_H. This change still doesn't write the PCI_IRQ register for all the PCI devices. We need to refactor the picasso pci_gpp code first. TEST=Boot majolica and see FCH IRQs being programmed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index a2f706f32b..50754a9e52 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -30,6 +30,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_NONCAR
+ select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select SOC_AMD_COMMON_BLOCK_SMBUS