summaryrefslogtreecommitdiff
path: root/src/soc/amd/cezanne/Kconfig
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-01-13 03:06:21 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-14 15:41:42 +0000
commit8a3d4d5ec6260a2db9cfda954860ed525bb67134 (patch)
treeb9d7574fbdd5d057547e4689017dd922701d70d2 /src/soc/amd/cezanne/Kconfig
parent91ef92525d8a9a0e83be8d91eb5e83b1cab58008 (diff)
soc/amd/cezanne: add console UART support
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index afee1efd70..f7f2d6898a 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -25,6 +25,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
+ select SOC_AMD_COMMON_BLOCK_UART
config CHIPSET_DEVICETREE
string
@@ -106,4 +107,10 @@ config MMCONF_BUS_NUMBER
int
default 64
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
+ hex
+ default 0xfedc9000 if UART_FOR_CONSOLE = 0
+ default 0xfedca000 if UART_FOR_CONSOLE = 1
+
endif # SOC_AMD_CEZANNE