diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-12 16:04:27 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-14 18:05:26 +0000 |
| commit | 35dc4b0ede0f4074351ac089d5abb1b5004cfa24 (patch) | |
| tree | 99f03fbd64261fe63ea31f043f4edb727c136b46 /src/soc/amd/cezanne/Kconfig | |
| parent | 394c6b092251f0da8f0bd159e0eb08a41a6e4afc (diff) | |
soc/amd/cezanne: Enable uCode update
TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 82ab3c40c3..9e5209f50e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -40,11 +40,14 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 5568 + config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" |