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authorRob Barnes <robbarnes@google.com>2021-04-15 17:21:19 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-04-22 12:43:33 +0000
commite09b681e6e574d0d59d260471c1ab91932fed48f (patch)
tree0c2271ea925642f44bd6328af5c0c60053045a6d /src/soc/amd/cezanne/Kconfig
parent03dfd19e6e941a32ae63ce5e20e6fb5438a25b06 (diff)
guybrush: Add Kconfig for PSP eSPI and port80
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 63baef8ea7..a8d025197d 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -279,6 +279,19 @@ config AMDFW_CONFIG_FILE
string
default "src/soc/amd/cezanne/fw.cfg"
+config PSP_DISABLE_POSTCODES
+ bool "Disable PSP post codes"
+ help
+ Disables the output of port80 post codes from PSP.
+
+config PSP_POSTCODES_ON_ESPI
+ bool "Use eSPI bus for PSP post codes"
+ default y
+ depends on !PSP_DISABLE_POSTCODES
+ help
+ Select to send PSP port80 post codes on eSPI bus.
+ If not selected, PSP port80 codes will be sent on LPC bus.
+
config PSP_LOAD_MP2_FW
bool
default n