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authorRaul E Rangel <rrangel@chromium.org>2021-05-05 13:30:10 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-05-06 23:30:55 +0000
commitd2d762a4c96587a8197a8e11706bda24e7a2200f (patch)
tree2d5bd5d24468f4152bea351fc5007f90fcca6818 /src/security
parentafe1fe55eb346cc5bee097dee75f5ccbe3b62df4 (diff)
soc/amd/common/espi: Print set eSPI peripheral config
This will print the config we are setting on the eSPI peripheral. e.g., Setting general configuration: slave: 0x98a00000 controller: 0xe2000000 eSPI Slave configuration: CRC checking enabled Dedicated Alert# used to signal alert event eSPI quad IO mode selected Only eSPI single IO mode supported Alert# pin is open-drain eSPI 33MHz selected eSPI up to 20MHz supported Maximum Wait state: 0 BUG=b:187122344, b:186135022 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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