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authorAngel Pons <th3fanbus@gmail.com>2021-01-29 11:35:16 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-30 23:14:08 +0000
commit9849488da1da669936a94f41db9b010eccca74a0 (patch)
tree81f870282113400fecdeb14c0c8e84659a58ec4e /src/security
parent90be7544e4089e3f140298620e23926a8c791760 (diff)
soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols. Change-Id: I88dcc0d5845198f668c6604c45fd869617168231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/security')
-rw-r--r--src/security/intel/stm/StmPlatformResource.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c
index 08b0bce1e9..a8da98ca09 100644
--- a/src/security/intel/stm/StmPlatformResource.c
+++ b/src/security/intel/stm/StmPlatformResource.c
@@ -98,7 +98,7 @@ MSR_TABLE_ENTRY msr_table[] = {
static void fixup_pciex_resource(void)
{
// Find max bus number and PCIEX length
- rsc_pcie_mmio.length = CONFIG_SA_PCIEX_LENGTH; // 0x10000000;// 256 MB
+ rsc_pcie_mmio.length = CONFIG_MMCONF_LENGTH; // 0x10000000;// 256 MB
rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS;
}