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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2019-05-29 23:38:15 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-07-31 04:27:00 +0000
commit047cac7b42eaf5b799e653ed1cc4a1b13e3f95e4 (patch)
tree1ec38be2b1dbe3ce7322c2d7f815bb4452f70f75 /src/security
parentb3cd762ea40dee1334932e683226b71cd23c43d9 (diff)
soc/intel/common/block: Enable PCH Thermal Sensor for threshold configuration
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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