diff options
| author | dnojiri <dnojiri@chromium.org> | 2020-04-03 10:51:50 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-04-17 22:01:28 +0000 |
| commit | 622c6b84ab029a366dd09740a24d36ae9fad697f (patch) | |
| tree | 0717b5d59c456a050697280fd50edcec176cfcea /src/security/tpm/tss/vendor | |
| parent | 3ed55e5da1ea3ed49a20aa3983fc6ac1bc366fb5 (diff) | |
TPM: Add tlcl_cr50_get_boot_mode
tlcl_cr50_get_boot_mode gets the boot mode from Cr50. The boot mode
tells coreboot/depthcharge whether booting the kernel is allowed or
not.
BUG=b:147298634, chromium:1045217, b:148259137
BRANCH=none
TEST=Verify software sync succeeds on Puff.
Signed-off-by: dnojiri <dnojiri@chromium.org>
Change-Id: Iadae848c4bf315f2131ff6aebcb35938307b5db4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40388
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security/tpm/tss/vendor')
| -rw-r--r-- | src/security/tpm/tss/vendor/cr50/cr50.c | 25 | ||||
| -rw-r--r-- | src/security/tpm/tss/vendor/cr50/cr50.h | 9 |
2 files changed, 34 insertions, 0 deletions
diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index ec69df4ac9..ae2f7c2516 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -107,6 +107,31 @@ uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode) return TPM_SUCCESS; } +uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode) +{ + struct tpm2_response *response; + uint16_t mode_command = TPM2_CR50_SUB_CMD_GET_BOOT_MODE; + + printk(BIOS_DEBUG, "Reading cr50 boot mode\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command); + + if (!response) + return TPM_E_IOERROR; + + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) + /* Explicitly inform caller when command is not supported */ + return TPM_E_NO_SUCH_COMMAND; + + if (response->hdr.tpm_code) + /* Unexpected return code from Cr50 */ + return TPM_E_IOERROR; + + *boot_mode = response->vcr.boot_mode; + + return TPM_SUCCESS; +} + uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms) { struct tpm2_response *response; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index e3137630de..0f91732856 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -15,6 +15,7 @@ #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) #define TPM2_CR50_SUB_CMD_TPM_MODE (40) +#define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52) /* Cr50 vendor-specific error codes. */ #define VENDOR_RC_ERR 0x00000500 @@ -79,6 +80,14 @@ uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode); /** + * CR50 specific TPM command sequence to query the current boot mode. + * + * Returns TPM_SUCCESS if boot mode is successfully retrieved. + * Returns TPM_E_* for errors. + */ +uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode); + +/** * CR50 specific TPM command sequence to trigger an immediate reset to the Cr50 * device after the specified timeout in milliseconds. A timeout of zero means * "IMMEDIATE REBOOT". |