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| author | Martin Roth <gaumless@gmail.com> | 2022-11-03 18:40:10 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-12 22:52:54 +0000 |
| commit | 9a8667a841f14af61f50a3fba4e0734f24ff24b2 (patch) | |
| tree | df0f9ec0fbc42b8263284ed577c87b85cb483775 /src/sbom/payload-skiboot.json | |
| parent | 898176a24c5bdde896a47bf60966d1476b4f913f (diff) | |
device & commonlib: Update pci_scan_bus postcodes
The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end
I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function. I don't think all three are needed.
0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code. Those postcodes should be adjusted to avoid conflicting.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/sbom/payload-skiboot.json')
0 files changed, 0 insertions, 0 deletions