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| author | Li Feng <li1.feng@intel.com> | 2024-02-27 21:47:15 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-20 21:57:27 +0000 |
| commit | 55a7d90a500782d861214ab743d860148465535a (patch) | |
| tree | bcf2cdc2a714488208d80028908b2f7c9243ebe6 /src/sbom/payload-SeaBIOS.json | |
| parent | 929ef5f7f1a3fb6155386d2f90f8f434ae02b6b6 (diff) | |
mb/google/brox: support ISH
Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main
firmware name so ISH shim loader can load firmware from file system.
ISH also need to be enabled if STORAGE_UFS is set.
BUG=b:280329972
TEST= Set bit CBI FW_CONFIG bit 21
Boot Brox board, check that ISH is enabled and loaded
lspci shows: 00:12.0 Serial controller: Intel Corporation Alder
Lake-P Integrated Sensor Hub (rev 01).
Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
Diffstat (limited to 'src/sbom/payload-SeaBIOS.json')
0 files changed, 0 insertions, 0 deletions