diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/pc80/i8259.c | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/pc80/i8259.c')
| -rw-r--r-- | src/pc80/i8259.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/pc80/i8259.c b/src/pc80/i8259.c index 330b7c6428..66988753cf 100644 --- a/src/pc80/i8259.c +++ b/src/pc80/i8259.c @@ -75,7 +75,7 @@ void setup_i8259(void) outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2); outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2); - /* Now the interrupt controller expects us to write to ICW3. + /* Now the interrupt controller expects us to write to ICW3. * * The normal scenario is to set up cascading on IRQ2 on the master * i8259 and assign the slave ID 2 to the slave i8259. @@ -89,9 +89,9 @@ void setup_i8259(void) * operating as part of an x86 architecture based chipset */ outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2); - outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); + outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); - /* Now clear the interrupts through OCW1. + /* Now clear the interrupts through OCW1. * First we mask off all interrupts on the slave interrupt controller * then we mask off all interrupts but interrupt 2 on the master * controller. This way the cascading stays alife. |