diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-12 01:49:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-19 17:00:50 +0200 |
| commit | ff1286d5003194bdbd78fd3b74d91bb01a77b399 (patch) | |
| tree | d4a6ac07c1467be8d9cc10d0b5f7122ccaffed1c /src/northbridge | |
| parent | 75f9131453c0e046f69ab4a8db7a3af7efcf6038 (diff) | |
nb/gm45,x4x/gma.c remove writes to nonexisting FDI registers
This removes writes to FDI related registers since there is no FDI
link on these targets. This is likely a remainder from copying code from
later targets.
TESTED on Thinkpad x200 (gm45)
Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16993
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/gm45/gma.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 6 |
2 files changed, 0 insertions, 18 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 30c8d9a6e1..8596193057 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -305,14 +305,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); @@ -598,14 +592,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 3f3ba2bf26..749a7c827a 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -311,14 +311,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + PIPE_LINK_M1(0), link_m1); write32(mmio + PIPE_LINK_N1(0), link_n1); - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |