diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-18 22:25:07 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:18:56 +0000 |
| commit | fa5ed059eb6fef1aa1681fbc7b38052b2028c1ac (patch) | |
| tree | 6dc67b2015e4f45b3cf842bda771d23ffd0c0848 /src/northbridge | |
| parent | e2531ffaa87be5c26005ff986db8492a03f809e3 (diff) | |
nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.
The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.
Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).
Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/quickpath.c | 28 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 1 |
2 files changed, 22 insertions, 7 deletions
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index e0e6f666b6..81621d2562 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <cpu/x86/msr.h> #include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -495,10 +497,20 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8) if (x1c04 != x1804 && x2ca8 == 0) mchbar_setbits8(0x2ca8, 1 << 0); + reg32 = 0x3000000; + if (info->revision >= 0x18 && qpi_pll_ratio <= 12) { + /* Get TDP limit in 1/8W units */ + const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT); + if ((msr.lo & 0x7fff) <= 90) + reg32 = 0; + } mchbar_write32(0x18d8, 0x120000); - mchbar_write32(0x18dc, 0x30a484a); + mchbar_write32(0x18dc, reg32 | 0xa484a); + + reg32 = qpi_pll_ratio > 20 ? 8 : 16; pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); - pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9404a | reg32 << 7); + mchbar_write32(0x18d8, 0x40000); mchbar_write32(0x18dc, 0xb000000); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); @@ -522,14 +534,18 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8) if (qpi_pll_ratio <= 14) reg8 = 0x33; - else if (qpi_pll_ratio <= 26) + else if (qpi_pll_ratio <= 22) reg8 = 0x42; else reg8 = 0x51; - mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60); - mchbar_setbits32(0x18b8, 0x200); - mchbar_setbits32(0x1918, 0x300); + info->fsb_frequency = qpi_pll_ratio * 15; + mchbar_write32(0x1a10, reg8 << 24 | info->fsb_frequency); + + if (info->silicon_revision == 2 || info->silicon_revision == 3) { + mchbar_setbits32(0x18b8, 0x200); + mchbar_setbits32(0x1918, 0x300); + } if (info->revision > 0x17) mchbar_setbits32(0x18b8, 0xc00); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 55c10b7e0b..fe67f0d0a3 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -2937,7 +2937,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) info.last_500_command[0] = 0; info.last_500_command[1] = 0; - info.fsb_frequency = 135 * 2; info.board_lane_delay[0] = 0x14; info.board_lane_delay[1] = 0x07; info.board_lane_delay[2] = 0x07; |